Positioning for the JPO's Digital Engineering Overview (Cordova / Neeld, 7 July 2025, Distribution A, Approval ID JSF25-0040): what they asked for, and what Siemens answers it with.
Unclassified throughoutFictional article: MSP-2No F-35 data used or implied
1Their own frame, read back to them
Read quickly, the JPO deck looks like an emulation buy. Cadence is the only vendor it names, Palladium for emulation, Protium for prototyping, and one verification-loop diagram is captioned as theirs. Opening on a tool-for-tool emulator fight concedes that frame and argues on the one box where the incumbent is already installed and funded.
Read closely, the deck's own findings are not about a missing emulator. In their words, the problems are a stove-piped development process, insufficient design verification, limited visibility into assembled hardware, and limited use of industry-standard tools and processes. The spine under their own future-state chart is "Digital Thread, Full Connectivity, Visibility and Authoritative Source of Truth."
Three consequences follow, and they define the demonstration:
Their own "closed feedback loop" slide cannot be closed by the vendor who drew it. That loop puts PLM at the top, running through verification automation, formal analysis, coverage-driven simulation, emulation, and continuous metrics. A pure-EDA vendor does not sell PLM, ALM, MBSE, multiphysics, or service lifecycle management. Siemens sells the EDA and the thing the loop closes into.
"Objective implementation readiness analysis with continuous metrics" is a standards problem stated as a tooling problem. It is ISO/IEC/IEEE 15288 clause 6.3.7 measurement, driven by 6.4.9 verification evidence, consumed by 6.3.2 project assessment and control. The readiness number in this demonstration is computed from evidence the customer can open, not asserted.
"Reduces dependence on industry" (Title 10) is a PLM argument, not an emulation argument. Organic capability means the government holds the authoritative source of truth, with supplier and OEM writing into it across a managed boundary. That is Teamcenter's home ground.
2The digital thread this demonstration proves
One design intent, carried through five systems without a re-entry point. This is the shape of the demonstration, and it is the shape of the closed-loop slide the JPO already drew.
Five systems, one thread. Teamcenter appears twice deliberately: once as the record the design lands in, once as the record the evidence returns to.
"Architecture Explorer" is Innexis Architect Explorer, the layer that gives the electronics a real hardware/software fidelity model: a modelled processor, real firmware binaries, and a licensed simulation run, not a block diagram. It sits between the system definition in Teamcenter and the detailed verification tools (Questa for RTL, Flotherm for thermal), and its own evidence lands back in Teamcenter on the same requirement ids as everything else.
3The one-line position
Cadence can emulate the card. Siemens can emulate the card and prove to a SETR board, from the authoritative source of truth, that the programme is ready, and the same thread carries it to flight test and through sustainment.
Three rows on the JPO's own IV&V techniques slide are where a pure-EDA vendor has no comparable answer at all: multi-mode analysis (power, thermal, EM), the quality system behind independent analysis, and the PLM backbone the whole loop depends on. Lead the technical portion of the demonstration there, not with emulation.
4The REMEDE pillars, mapped
Answer column leads with the capability; the underpinning Siemens technology follows it. Clause column is mapped against the ISO/IEC/IEEE 15288 systems-engineering standard the JPO's own review process is measured against.
What they asked for
Siemens answer
Clause
Hardware-accurate digital twin: early HW/SW system integration and co-development
Virtual system integration and early hardware/software co-development, on Innexis Architect Explorer (which ran here) with Innexis VSI behind it at system-of-systems scale (which did not), plus Questa for RTL simulation and Catapult for HLS
6.4.7, 6.4.8
Comprehensive verification: continuous metric-driven assessment against implementation readiness
The demonstration's centre. Continuous, metric-driven verification against every requirement: functional coverage and formal analysis (Questa), multi-mode analysis (Flotherm), and hardware/software co-analysis (Innexis), all landed as evidence and rolled into a computed readiness record
6.4.9, 6.3.7, 6.3.2
Commercial best practice: modernize defense-industrial-base development and sustainment
A shared, managed source of truth across Supplier / OEM / Gov boundaries, built on Teamcenter
6.1.1, 6.1.2, 6.3.6
Verification plan automation
Verification method assignment against every requirement, generating the plan rather than authoring it by hand, in Teamcenter Systems Engineering
6.4.9 outcome a
Reduced cost / schedule through digital twins
Cost and schedule visibility, through Teamcenter Cost Rollup and Program Planning / IPP&E
6.4.6, 6.3.1
5Their IV&V techniques, technique by technique
Their claim is that combining techniques moves verification coverage on complex devices from 10–20% to 60–80%. The demonstration reproduces that arithmetic on real evidence rather than asserting it: see the stage table.
Technique
Siemens answer
Competitive parity
Dynamic analysis (simulation, UVM)
Functional coverage, via Questa
parity, argue on merit
Static techniques (formal, lint)
Formal and clock-domain verification, via the Questa formal / autocheck / CDC family
parity, argue on merit
HW/SW co-analysis (emulation & prototyping)
Software executing against the hardware, shown two ways here: a SystemC/TLM virtual platform on Questa, and our own OFP on a modelled processor in Innexis Architect Explorer. Innexis Virtual System Interconnect is the product that scales the same technique to a system of systems, and it is proposed rather than run
reframed: integration before hardware exists, not "whose emulator is faster"
Multi-mode analysis (power, thermal, EM)
Strongest column. Thermal, signal/power-integrity, and structural analysis, via Flotherm / Flotherm XT, HyperLynx, and Simcenter 3D, all managed through Teamcenter SPDM
no comparable answer from a pure-EDA vendor
Independent analysis (security, safety)
Security property checking and safety FMEA, via Questa formal methods and Teamcenter Quality
no comparable quality system
6The article: MSP-2
The MSP-2 mission systems processor DMSMS refresh: a fictional radar signal-processing card whose primary FPGA has gone end-of-life, carried as a subsystem of a platform architecture authored on the demonstration tier for the purpose. Two candidates: a pin-compatible part swap (Candidate A) and an SoC consolidation (Candidate B). Unclassified throughout; no F-35 data of any kind is used or implied.
Chosen because it is the customer's own stated problem (DMSMS refresh), because it forces all five of their IV&V techniques to be genuinely necessary, and because two candidates on a shared parent is what makes the trade-study machinery real instead of a single-option walkthrough. A pin-compatible part swap is also the case that most rewards this stack specifically: pin compatibility says nothing about internal die architecture, and a physics-only review would never be positioned to catch that gap.
The readiness argument in this demonstration is not a slide of claims. Every row below is either a real run against the real article, with a result the customer can open and re-check, or it is marked as what we would propose. The two lists are drawn in different colours on purpose, and a customer who later discovers we blurred them loses the one thing this demonstration is trying to buy.
Proven: it ran here, and it was measured
Claim
Evidence
The evidence lives in Teamcenter, not in a folder
RUN. 18 datasets attached to 23 verification objects by 110 links, all 18 verified by hash of bytes fetched back out of the file store. The 72 constructed readiness records were deliberately left out, so the gap is visible rather than dressed as audited.
Thermal verification of the MSP-2 card, on Simcenter Flotherm 2604
RUN 110.12 °C measured on a real solver, converged, and it corrected our own slide, which read 111.8 from constructed data
Functional coverage and formal verification of the MSP-2 datapath, on Questa Sim-64 2026.2
RUN real report files, real coverage database
Hardware and software co-analysis: an OFP model on a SystemC/TLM-2.0 virtual platform against the unmodified MSP-2 RTL, Questa Sim-64 2026.2
RUN 2.500000 GSPS, 0 ICD deviations over 23 checks, with in-run controls and two defect runs that failed as they should
Headless hardware and software twin of the MSP-2, on Innexis Architect Explorer 2026.1
RUN licensed as VelSysExplorer, our own OFP cross-compiled to aarch64 on a modelled quad-core Cortex-A53 under Nucleus RTOS, 13 of 13 measurement points agreeing with an independent reference
Requirements, verification matrix, both candidate architectures and the mission layer as native Teamcenter 2606 objects, rolling up in both carriers
RUN read back from the tier, counted from a second process with its own login
Reduced-order modelling toolchain, on Simcenter romAI
RUN 4 ROMs trained, 4 FMI 2.0 FMUs exported and stepped. And they fit badly: every ROM scores worse than a constant predictor on a held-out block, while the Python concept model reproduces the same holdout bit-exactly. Both halves travel together
Transition, operation, and sustainment coverage, across the Xcelerator portfolio
CONFIRMED Teamcenter SLM (Service Manager, Service Planner, Service Engineering, As-Built Manager), plus Opcenter Maintenance Execution, Insights Hub, and Capital Publisher. A portfolio claim, not a Teamcenter-alone one
Proposed: the product answer, which did not run here
Claim
Status
Innexis Virtual System Interconnect, for system-of-systems virtual integration at scale
NOT RUN the standalone tree is installed and will not license: its SALT client rejects this site's certificate, which the Architect Explorer install accepts. A certificate format, not an entitlement, so the fix is a re-issued licence rather than a purchase. It produced nothing here
Capital, for the DESIL modular interface architecture
AUTHORED, NOT MATERIALIZED the interface bundles validate against Capital's own validator and the project XML is generated and checked, but the import step needs the Capital GUI and no Capital licence checkout was demonstrated on this machine
HyperLynx and Simcenter 3D, for the signal-integrity and vibration halves of the multi-mode column
NOT INSTALLED thermal is the multi-mode technique that ran here. The column is our strongest and it is shown one technique wide, not three
Veloce, for hardware-assisted emulation
NOT AVAILABLE emulation hardware is a rack rather than an install. This is the incumbent's ground and we are not pretending to have run it
And the number refuses to move, which is the point. Computed on the real evidence alone, the record still abstains: coverage is under the declared abstention floor, co_analysis sits at 3 of 6, and the gate reads NOT ASSESSED. Adding a second co-simulation tool did not move it, measured three ways, because coverage counts requirement-and-technique pairs and both tools answer the same three requirements. A figure that declines to improve when you add a tool is the proof that it is computed rather than staged.
